Flip-chip interconnect technology for molded flip-chip semiconductor packages involves depositing solder bumps on the pads of a semiconductor die. The die is mounted to the leadframe by flipping the die over so that its top side faces down, and aligned so that its pads align with matching leads of the leadframe. The solder is then reflowed to complete the interconnect, or alternatively, if the flip chip uses diffusion bonding method then no reflow is required. This is in contrast to wire bonding, in which the die is mounted upright and wires are used to interconnect the die pads to the leadframe.
Conventional molded flip-chip semiconductor packages have a lead spacing (B) to leadframe thickness (A) ratio of B/A>1, meaning that the lead spacing depends directly on the leadframe thickness. Thin leadframes cannot be used for many types of semiconductor devices such as power devices, limiting the amount by which certain types of semiconductor dies can shrink in size for molded flip-chip semiconductor packages. Die placement tolerance is often imprecise e.g. +/−0.050 mm, requiring a large area for placing semiconductor dies on leadframes. This in turn further limits any die size reductions that can be practically realized. As such, there is a need for reducing the lead spacing without reducing leadframe thickness. Also with conventional leadframe technologies, the semiconductor die size cannot be reduced without also reducing the footprint of the package which in turn is controlled by the end customer PCB (printed circuit board) footprint.